SONG'S LYRIC-SUMMER OF 69

I got my first real six-string
Bought it at the five-and-dime
Played it till my fingers bled
It was the summer of 69

Me and some guys from school
Had a band and we tried real hard
Jimmy quit and jody got married
I shoulda known wed never get far
Oh when I look back now
That summer seemed to last forever
And if I had the choice
Ya - Id always wanna be there
Those were the best days of my life

Aint no use in complainin
When you got a job to do
Spent my evenins down at the drive-in
And thats when I met you

Standin on your mamas porch
You told me that youd wait forever
Oh and when you held my hand
I knew that it was now or never
Those were the best days of my life

Back in the summer of 69

Man we were killin time
We were young and restless
We needed to unwind
I guess nothin can last forever - forever, no

And now the times are changin
Look at everything thats come and gone
Sometimes when I play that old six-string
I think about ya wonder what went wrong

Standin on your mamas porch
You told me it would last forever
Oh the way you held my hand
I knew that it was now or never
Those were the best days of my life

Back in the summer of 69

SONG'S LYRIC-WALK ALONE

I walk a lonely road
The only one that I have ever known
Don't know where it goes
But it's home to me and I walk alone

I walk this empty street
On the Boulevard of Broken Dreams
Where the city sleeps
and I'm the only one and I walk alone

I walk alone
I walk alone

I walk alone
I walk a...

My shadow's the only one that walks beside me
My shallow heart's the only thing that's beating
Sometimes I wish someone out there will find me
'Til then I walk alone

Ah-ah, Ah-ah, Ah-ah, Aaah-ah,
Ah-ah, Ah-ah, Ah-ah

I'm walking down the line
That divides me somewhere in my mind
On the border line
Of the edge and where I walk alone

Read between the lines
What's fucked up and everything's alright
Check my vital signs
To know I'm still alive and I walk alone

I walk alone
I walk alone

I walk alone
I walk a...

My shadow's the only one that walks beside me
My shallow heart's the only thing that's beating
Sometimes I wish someone out ther

SONG'S LYRIC-NUMB

I'm tired of being what you want me to be
feeling so faithless
lost under the surface
I don't know what you're expecting of me
put under the pressure
of walking in your shoes
[caught in the undertow, just caught in the undertow]
every step that I take is another mistake to you
[caught in the undertow, just caught in the undertow]

I've
become so numb
I can't feel you there
become so tired
so much more aware
I'm becoming this
all I want to do
is be more like me
and be less like you.

can't you see that you're smothering me
holding too tightly
afraid to lose control
cause everything that you thought I would be
is falling apart right in front of you.

[caught in the undertow, just caught in the undertow],
every step that I take is another mistake to you
[caught in the undertow,just caught in the undertow]
and every second I waste is more than I can take.

I've
become so numb
I can't feel you there
become so tired
so much more aware
I'm becoming this
all I want to do
is be more like me
and be less like you.

And I know
I may end up failing too

But I know
you were just like me
with someone disappointed in you.

I've
become so numb
I can't feel you there
become so tired
so much more aware
I'm becoming this
all I want to do
is be more like me
and be less like
I've
become so numb
I can't feel you there
[tired of being what you want me to be]
(repeat x 2)

STUDY NOTES-8085 MICROPROCESSOR

Tutorial
On
Introduction to 8085 Architecture and Programming
Contents
1. Internal architecture of 8085 microprocessor
2. 8085 system bus
3. 8085 pin description.
4. 8085 functional description.
5. Programming model of 8085 microprocessor
6. Addressing modes.
7. Instruction set classification.
8. Instruction format.
9. Sample programs.
1. Internal Architecture of 8085 Microprocessor
Control Unit
Generates signals within uP to carry out the instruction, which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.
Arithmetic Logic Unit
The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to perform
arithmetic. Always stores result of operation in Accumulator.
Registers
The 8085/8080A-programming model includes six registers, one accumulator, and
one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack
pointer and the program counter. They are described briefly as follows.
The 8085/8080A has six general-purpose registers to store 8-bit data; these are
identified as B,C,D,E,H, and L as shown in the figure. They can be combined as
register pairs - BC, DE, and HL - to perform some 16-bit operations. The
programmer can use these registers to store or copy data into the registers by using
data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are
listed in the Table and their bit positions in the flag register are shown in the Figure
below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor
uses these flags to test data conditions.
For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is
set to one. When an arithmetic operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five bit
positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the micro-
processor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough understanding
of flag is essential in writing assembly language programs.
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the
next byte is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer. The stack concept is explained
in the chapter "Stack and Subroutines."
Instruction Register/Decoder
Temporary store for the current instruction of a program. Latest instruction sent here
from memory prior to execution. Decoder then takes instruction and ‘decodes’ or
interprets the instruction. Decoded instruction then passed to next stage.
Memory Address Register
Holds address, received from PC, of next program instruction. Feeds the address bus
with addresses of location of the program under execution.
Control Generator
Generates signals within uP to carry out the instruction which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.
Register Selector
This block controls the use of the register stack in the example. Just a logic circuit
which switches between different registers in the set will receive instructions from
Control Unit.
General Purpose Registers
uP requires extra registers for versatility. Can be used to store additional data during a
program. More complex processors may have a variety of differently named registers.
Microprogramming
How does the µP knows what an instruction means, especially when it is only a
binary number? The microprogram in a uP/uC is written by the chip designer and tells
the uP/uC the meaning of each instruction uP/uC can then carry out operation.
2. 8085 System Bus
Typical system uses a number of busses, collection of wires, which transmit binary
numbers, one bit per wire. A typical microprocessor communicates with memory and
other devices (input and output) using three busses: Address Bus, Data Bus and
Control Bus.
Address Bus
One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts
memory to ‘open’ the designated box. Data (binary) can then be put in or taken
out.The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A
16 bit binary number allows 216 different numbers, or 32000 different numbers, ie
0000000000000000 up to 1111111111111111. Because memory consists of boxes,
each with a unique address, the size of the address bus determines the size of memory,
which can be used. To communicate with memory the microprocessor sends an
address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. The
memory the selects box number 3 for reading or writing data. Address bus is
unidirectional, ie numbers only sent from microprocessor to memory, not other way.
Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits),
how many wires does the address bus need, in order to be able to specify an address in
this memory? Note: the memory is organized in groups of 8 bits per location,
therefore, how many locations must you be able to specify?
Data Bus
Data Bus: carries ‘data’, in binary form, between µP and other external units, such as
memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory and
µP size helps determine performance of µP. The Data Bus typically consists of 8
wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data",
ie information, results of arithmetic, etc, between memory and the microprocessor.
Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If
only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger
number have to be broken down into chunks of 255. This slows microprocessor. Data
Bus also carries instructions from memory to the microprocessor. Size of the bus
therefore limits the number of possible instructions to 256, each specified by a
separate number.
Control Bus
Control Bus are various lines which have specific functions for coordinating and
controlling uP operations. Eg: Read/NotWrite line, single binary digit. Control
whether memory is being ‘written to’ (data stored in mem) or ‘read from’ (data taken
out of mem) 1 = Read, 0 = Write. May also include clock line(s) for
timing/synchronising, ‘interrupts’, ‘reset’ etc. Typically µP has 10 control lines.
Cannot function correctly without these vital control signals.
The Control Bus carries control signals partly unidirectional, partly bi-directional.
Control signals are things like "read or write". This tells memory that we are either
reading from a location, specified on the address bus, or writing to a location
specified. Various other signals to control and coordinate the operation of the system.
Modern day microprocessors, like 80386, 80486 have much larger busses. Typically
16 or 32 bit busses, which allow larger number of instructions, more memory
location, and faster arithmetic. Microcontrollers organized along same lines, except:
because microcontrollers have memory etc inside the chip, the busses may all be
internal. In the microprocessor the three busses are external to the chip (except for the
internal data bus). In case of external busses, the chip connects to the busses via
buffers, which are simply an electronic connection between external bus and the
internal data bus.
3. 8085 Pin description.
Properties
Single + 5V Supply
4 Vectored Interrupts (One is Non Maskable)
Serial In/Serial Out Port
Decimal, Binary, and Double Precision Arithmetic
Direct Addressing Capability to 64K bytes of memory
The Intel 8085A is a new generation, complete 8 bit parallel central processing unit
(CPU). The 8085A uses a multiplexed data bus. The address is split between the 8bit
address bus and the 8bit data bus. Figures are at the end of the document.
Pin Description
The following describes the function of each pin:
A6 - A1s (Output 3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.
AD0 - 7 (Input/Output 3state)
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)
appear on the bus during the first clock cycle of a machine state. It then becomes the
data bus during the second and third clock cycles. 3 stated during Hold and Halt
modes.
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state and
enables the address to get latched into the on chip latch of peripherals. The falling
edge of ALE is set to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.
RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the Data
Bus is available for the data transfer.
WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory
or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt
modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data
Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as
soon as the completion of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and
that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA goes
low.
INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only
during the next to the last clock cycle of the instruction. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During
this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt
service routine. The INTR is enabled and disabled by software. It is disabled by Reset
and immediately after an interrupt is accepted.
INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD
during the Instruction cycle after an INTR is accepted. It can be used to activate the
8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except
they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as
INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of
any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA
flipflops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)
Indicates CPlJ is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.
X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can also be
an external clock input instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and
Halt modes.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a
RIM instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.
Vcc
+5 volt supply.
Vss
Ground Reference.

4. 8085 Functional Description
The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt
supply. Its basic clock speed is 3 MHz thus improving on the present 8080's
performance with higher system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.
The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit
Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address
is sent out. The lower 8bits are latched into the peripherals by the Address Latch
Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory
or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are
synchronized. The 8085A also provides serial input data (SID) and serial output data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts and one
non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus
control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status strobe.
The status is partially encoded, and provides the user with advanced timing of the
type of bus transfer being done. IO/M cycle status signal is provided directly also.
Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH
S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address
are multiplexed with the data instead of status. The ALE line is used as a strobe to
enter the lower half of the address into the memory or peripheral address latch. This
also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O
The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR
is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5.
7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable.
The three RESTART interrupts cause the internal execution of RST (saving the
program counter in the stack and branching to the RESTART address) if the interrupts
are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the
internal execution of a RST independent of the state of the interrupt enable or masks.
The interrupts are arranged in a fixed priority that determines which interrupt is to be
recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,
RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into
account the priority of a routine that was started by a higher priority interrupt. RST
5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of
the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as
power failure or bus error. The TRAP input is recognized just as any other interrupt
but has the highest priority. It is not affected by any flag or mask. The TRAP input is
both edge and level sensitive.
Basic System Timing
The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower
8bits of address on the Data Bus. Figure 2 shows an instruction fetch, memory read
and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O
port address is copied on both the upper and lower half of the address. As in the 8080,
the READY line is used to extend the read and write pulse lengths so that the 8085A
can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is
through with it by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to the
8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and
8355 will have the following features:
· 2K Bytes ROM
· 256 Bytes RAM
· 1 Timer/Counter
· 4 8bit l/O Ports
· 1 6bit l/O Port
· 4 Interrupt Levels
· Serial In/Serial Out Ports
In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing
technique. With this technique, an area of memory address space is assigned for l/O
address, thereby, using the memory address for I/O manipulation. The 8085A CPU
can also interface with the standard memory that does not have the multiplexed
address/data bus.

5. The 8085 Programming Model
In the previous tutorial we described the 8085 microprocessor registers in reference to
the internal data operations. The same information is repeated here briefly to provide
the continuity and the context to the instruction set and to enable the readers who
prefer to focus initially on the programming aspect of the microprocessor.
The 8085 programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer
and the program counter. They are described briefly as follows.
Registers
The 8085 has six general-purpose registers to store 8-bit data; these are identified as
B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs -
BC, DE, and HL - to perform some 16-bit operations. The programmer can use these
registers to store or copy data into the registers by using data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
ACCUMULATOR A (8) FLAG REGISTER
B (8)
D (8)
H (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
C (8)
E (8)
L (8)
Data Bus Address Bus
16 Lines unidirectional 8 Lines Bidirectional
Flags
The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit
positions in the flag register are shown in the Figure below. The most commonly used
flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions.
For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is
set to one. When an arithmetic operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five bit
positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the micro-
processor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough understanding
of flag is essential in writing assembly language programs.
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the
next byte is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer.
This programming model will be used in subsequent tutorials to examine how these
registers are affected after the execution of an instruction.
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
6. The 8085 Addressing Modes
The instructions MOV B, A or MVI A, 82H are to copy data from a source into a
destination. In these instructions the source can be a register, an input port, or an 8-bit
number (00H to FFH). Similarly, a destination can be a register or an output port. The
sources and destination are operands. The various formats for specifying operands are
called the ADDRESSING MODES. For 8085, they are:
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
Immediate addressing
Data is present in the instruction. Load the immediate data to the destination provided.
Example: MVI R,data
Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs
Direct addressing
Used to accept data from outside devices to store in the accumulator or send the data
stored in the accumulator to the outside device. Accept the data from the port 00H and
store them into the accumulator or Send the data from the accumulator to the port
01H.
Example: IN 00H or OUT 01H
Indirect Addressing
This means that the Effective Address is calculated by the processor. And the
contents of the address (and the one following) is used to form a second address. The
second address is where the data is stored. Note that this requires several memory
accesses; two accesses to retrieve the 16-bit address and a further access (or accesses)
to retrieve the data which is to be loaded into the register.
7. Instruction Set Classification
An instruction is a binary pattern designed inside a microprocessor to perform a
specific function. The entire group of instructions, called the instruction set,
determines what functions the microprocessor can perform. These instructions can be
classified into the following five functional categories: data transfer (copy)
operations, arithmetic operations, logical operations, branching operations, and
machine-control operations.
Data Transfer (Copy) Operations
This group of instructions copy data from a location called a source to another
location called a destination, without modifying the contents of the source. In
technical manuals, the term data transfer is used for this copying function. However,
the term transfer is misleading; it creates the impression that the contents of the
source are destroyed when, in fact, the contents are retained without any modification.
The various types of data transfer (copy) are listed below together with examples of
each type:
Types
Examples
1. Between Registers.
1. Copy the contents of the register B into
register D.
2. Specific data byte to a register or a
memory location.
2. Load register B with the data byte 32H.
3. Between a memory location and a
register.
3. From a memory location 2000H to register
B.
4. Between an I/O device and the
accumulator.
4.From an input keyboard to the
accumulator.
Arithmetic Operations
These instructions perform arithmetic operations such as addition, subtraction,
increment, and decrement.
Addition - Any 8-bit number, or the contents of a register or the contents of a
memory location can be added to the contents of the accumulator and the sum is
stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the
contents of register B cannot be added directly to the contents of the register C). The
instruction DAD is an exception; it adds 16-bit data directly in register pairs.
Subtraction - Any 8-bit number, or the contents of a register, or the contents of a
memory location can be subtracted from the contents of the accumulator and the
results stored in the accumulator. The subtraction is performed in 2's compliment, and
the results if negative, are expressed in 2's complement. No two other registers can be
subtracted directly.
Increment/Decrement - The 8-bit contents of a register or a memory location can be
incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such
as BC) can be incremented or decrement by 1. These increment and decrement
operations differ from addition and subtraction in an important way; i.e., they can be
performed in any one of the registers or in a memory location.
Logical Operations
These instructions perform various logical operations with the contents of the
accumulator.
AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of
a memory location can be logically ANDed, Ored, or Exclusive-ORed with the
contents of the accumulator. The results are stored in the accumulator.
Rotate- Each bit in the accumulator can be shifted either left or right to the next
position.
Compare- Any 8-bit number, or the contents of a register, or a memory location can
be compared for equality, greater than, or less than, with the contents of the
accumulator.
Complement - The contents of the accumulator can be complemented. All 0s are
replaced by 1s and all 1s are replaced by 0s.
Branching Operations
This group of instructions alters the sequence of program execution either
conditionally or unconditionally.
Jump - Conditional jumps are an important aspect of the decision-making process in
the programming. These instructions test for a certain conditions (e.g., Zero or Carry
flag) and alter the program sequence when the condition is met. In addition, the
instruction set includes an instruction called unconditional jump.
Call, Return, and Restart - These instructions change the sequence of a program
either by calling a subroutine or returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.
Machine Control Operations
These instructions control machine functions such as Halt, Interrupt, or do nothing.
The microprocessor operations related to data manipulation can be summarized in
four functions:
1. copying data
2. performing arithmetic operations
3. performing logical operations
4. testing for a given condition and alerting the program sequence
Some important aspects of the instruction set are noted below:
1. In data transfer, the contents of the source are not destroyed; only the contents of
the destination are changed. The data copy instructions do not affect the flags.
2. Arithmetic and Logical operations are performed with the contents of the
accumulator, and the results are stored in the accumulator (with some
expectations). The flags are affected according to the results.
3. Any register including the memory can be used for increment and decrement.
4. A program sequence can be changed either conditionally or by testing for a given
data condition.
8. Instruction Format
An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the
operation code (opcode), and the second is the data to be operated on, called the
operand. The operand (or data) can be specified in various ways. It may include 8-bit
(or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-bit) address.
In some instructions, the operand is implicit.
Instruction word size
The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.
However, instructions are commonly referred to in terms of bytes rather than words.
One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s)
are internal register and are coded into the instruction.
For example:
Task Op
code
Operand Binary
Code
Hex
Code
Copy the contents of the accumulator in
the register C.
MOV C,A 0100 1111 4FH
Add the contents of register B to the
contents of the accumulator.
ADD B 1000 0000 80H
Invert (compliment) each bit in the
accumulator.
CMA 0010 1111 2FH
These instructions are 1-byte instructions performing three different tasks. In the first
instruction, both operand registers are specified. In the second instruction, the operand
B is specified and the accumulator is assumed. Similarly, in the third instruction, the
accumulator is assumed to be the implicit operand. These instructions are stored in 8-
bit binary format in memory; each requires one memory location.
MOV rd, rs
rd <-- rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is
the destination of the data, sss is the code of the source register.
Example: MOV A,B
Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction
design of such processors).
ADD r
A <-- A + r
Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second
byte specifies the operand. Source operand is a data byte immediately following the
opcode. For example:
Task Opcode Operand Binary
Code
Hex Code
Load an 8-bit data
byte in the
accumulator.
MVI A, Data 3E
Data
First Byte
Second Byte
Assume that the data byte is 32H. The assembly language instruction is written as
Mnemonics Hex code
MVI A, 32H 3E 32H
The instruction would require two memory locations to store in memory.
MVI r,data
r <-- data
Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an
example of immediate addressing.
ADI data
A <-- A + data
OUT port
0011 1110
DATA
where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but
points directly to where it is located this is called direct addressing.
Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two
bytes specify the 16-bit address. Note that the second byte is the low-order address
and the third byte is the high-order address.
opcode + data byte + data byte
For example:
Task Opcode Operand Binary code Hex Code
Transfer the
program
sequence to
the memory
location
2085H.
JMP 2085H C3
85
20
First byte
Second Byte
Third Byte
This instruction would require three memory locations to store in memory.
Three byte instructions - opcode + data byte + data byte
LXI rp, data16
rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data
bytes are 16-bit data in L H order of significance.
rp <-- data16
Example:
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate
addressing.
LDA addr
A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as
3AH 34H 21H. This is also an example of direct addressing.
9. Sample Programs
Write an assembly program to add two numbers
Program
MVI D, 8BH
MVI C, 6FH
MOV A, C
1100 0011
1000 0101
0010 0000
ADD D
OUT PORT1
HLT
Write an assembly program to multiply a number by 8
Program
MVI A, 30H
RRC
RRC
RRC
OUT PORT1
HLT
Write an assembly program to find greatest between two numbers
Program
MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC GRT
OUT PORT1
HLT
EQU: MVI A, 01H
OUT PORT1
HLT
GRT: MOV A, C
OUT PORT1
HLT

STUDY NOTES-Networking

Networking

Network is an integrated communication system where different user can exchange data or message.

Computer Network:

Our computer network is inter-connection of different individual computer device using hardware and software resource for the exchanging data or information.

Features of computer network:

1). Line configuration 2. Networking topology 3). Network category 4). Internetworking

5) Transmission media.

Line configuration:

It denotes the types of connection required between the devices for communication. These can be of two fundamental types.

(a) Point- to- point:- These means there is a dedicated line between a particular pair of device.

b)Multi –point: - this means using a common line (BUS). We can connect multiple devices for there inter communication

Network topology:-

Means categorizing network ware to geographical pattern

Mesh denotes direct connection between every individual device it there are n-devices we required N(N-1)/2 connection.

In Bus topology a carrier bus as a communication line connects different devices

In star topology a server acts as a center point to connected different devices.

It in star network every device is connected to left and right neighbour only it forms a ring network.

In tree topology servers are connected to devices using a particular hierarchical manner.

Network category:- Network can be categories according to the area covers by the network. The categories are as follows.

1) Local area network 2) Metropolitan area network 3)Wide area network 4)Global area network.

LAN:- It is a localized network system which comprises of either a small area or a building etc. It consists of a server, which is connected to set of nodes via and electronic device called HUB. Any message or data from server is related the nodes with specific nodes address. The connection is mostly done by using copper cable.

MAN:- different LAN servers in metropolitan city can be inter connected using a master server to create a MAN. These type of network spreads over a city and the connection is done mainly through cables of some times using wireless technology.

WAN:- it is inter city network system to connect different city servers using a master server such network uses connection oriented of connection less technology for connecting different devices and servers. Normally, WAN consist of a single country or a set of country eg. Indian railway reservation system.

GAN:- Inter connecting different WAN creates a globalised network. Which may spread over the globe. Such network mostly uses satellite technology and also connection-oriented technology to perform inter communication. One of the popular examples of such network to Internet.

Transmission Mode:- Transmission mode determines the direction of data flow in case of a communication system.

1) Simplex mode: These systems provides ones specific device to send data and mother specific device to receive data ex. T.V.

2) Half duplex mode:- Here data can flow in both direction but in one specific direction at a time. Ex. Walkie talkie.

3) Full duplex mode:- here data can flow in both direction simultaneously eg. Telephone.

Inter networking:- different network when inter connected either locally or in a wide area, the conception is called internetworking. So, basically network - to – network integration using wireless or wire technology creates Internetwork. Eg. BSNL.

OSI [Open system interconnection]: - ISO has proposed a standard network interfacing software model, for intercommunication between different devices. Such software model is called OSI model. OSI model is a set of specification about standard network software.

1. Application layer 2. presentation layer 3. session layer 4. transport layer 5. network layer 6. data link layer 7. physical layer

In these layer structure lower layer provides basic circuits to its immediate upper layer and the interaction between layers is level by level.

PHYSICAL LAYER: these layer provides specification about physical characteristics like. Voltage to be used, type of signal, how bits will be convert, type of carrier including hardware characteristics are define in these layer.

Data link layer: These layer is responsible for converting signal pattern to its equivalent meaningful binary format to represent data. These includes representation of voltage pattern, specification indicating which voltage represent 1 or which represent o.

(1) Inter-conversion from signal pattern to data form and viceversa.

(2) To check is the send data has been actually received on the receiver side, These layer perform error control activity.

(3) To match the speed of senders transmission with that of receiver. These layer uses flow control mechanism, otherwise there is a possibility of data loss.

NIC: Network interface card

(4) For every machine in a network, there exists two types of address to identify the machine.

(a) physical address denotes a particular electronic circuit or chip no, which is called network interface card, which is a circuit for enabling a machine connected to a network.

(b) When a machine is connected to a server. The server provides local address logical address for a particular node or client.

Such addressing in a network is responsibility of there layer.

Network layer: These layer is responsible for mode-to-node delivery of data packet for transmission of data. The basic function are as follows:

(i) It provides another logical address where data packet is crossing a country or in case of international transmission system.

(ii) These layer to decides cost and time optimized route for transporting data over the network.

Transport layer: These layer responsible for end-to-end delivery of data packet in a network. The basic functions are as follows:

(i) When large amount(vol) of data is required to be transmitted, it is broken up into small parts or pieces, individual piece are transmitted individually. On the receiver side the pieces are to be rearranged to make out original data. These is a vital responsibility of these layer.

(ii) It performs flow control and error control to avoid data loss in case of end-to-end communication.

(iii) For communication of data connection protocol is used before actual communication. The protocol includes connection establishment data transfer and connection termination. All these are perform by transport layer.

Session Layer: These layer performs same basic transmission activity as follows:

(i) It controls process-to-process communication in a network. A process is identified by service access point address(SAP), which is a running programmed.

(ii) It keeps synchronization points for a long data transmission process to keep track of last successful transmission of data packet.

Presentation Layer: These layer performs manipulation of the content of data for over coming different language problem or to introduce data security.

The basic function are as follows:

(i) Different user may use local language, which is must compatible with another user. These layer converts data contents to a global format, transport formatted data over the network, and converts back to local format on the receivers .

(ii) transmitted data may be trapped or used by any unauthorized user which is a problem for data security. Network uses enayption description mechanism to convert data to meaningless form, transmit it over the line and convert back in the receivers end. These mechanism is supported by these layer.

Application Layer: These layer enables human user to access network. It provide a software called network browser, which is used to access a particular network site. Also, the layer provides basic facilities which are as follows:

(i) e-mail: These is a mail delivery service by which user can send or receive mails.

(ii) FTAM: stands for file transfer access management. These is a file handling service to transmit electronic files.

Signal: Signal is a kind of electro- magnetic wave or pattern, which depends on the type of carrier used.

Transmission medium: transmission medium are communication system carriers, which transport signal from sender to receiver device. It can be characterized in two types:

Guided medium: Gm uses physical conducting wires to transmit signals. It is of three types.

(a) Twisted pair wire(b) co-axial cable(c) optical fibre/Fibre optic cable

Twisted pair wire consists of two copper insulated wires would around each other. Twisted pair wire are of two types:

(i) Shielded Twisted pair wire(STP): STP cable has a mesh covering over the twisted pair wires. TP without the outer covering is unshielded.

(j) Unshielded medium: when multiple twisted pair wire are kept transmitted signals can create electric magnetic interreference giving rise to unwanted energy or voltage called cross-talk. These can be avoids by using shielded twisted wire pair.

Co-oxial cable: Co-oxial cable consists of a set of twisted pair wire around a central axis. It is used to carry high values of signal using different frequency. Ex: cable(TV)

Two types:

(1) base band cable: These type of cables carry digital signal will less frequency level.

(2) Broad-band: It carries analog signal with higher frequency.

Fibre-Optic cable: It uses glass medium to transmit signals in the form of light wave. Actually, optical source in used to generate light, the cable is surrounded by rarer glass medium, so that using reflection entire light wave is kept inside the medium and propagated.

Two type:

(1) single mode fibre: uses single light source.

(2) Multi mode fibre: uses multiple light source.

Unguided medium: Uses wireless communication to transmit signals using air medium.

Radio wave communication: These are low frequency signal which can bend when it faces curvature.

Types of RW transmission:

(a) surface propagation: It are low frequency signals travels close to earth surface, the signal can propagate ignoring curvature of the surface.

(b) Tropospheric Propagation: there radio waves are directed toward tropospheric layer and reflected back to the receiving side.

In these case the transmission is line-of-sight type bicog bending is not allow.

(c) Ionospheric propagation: radio waves are transmitted upword, reflected by ionospheric and comes done in and there part of the earth surface.

(d) Space Propagation: These uses satellite communication where gio-stationary satellite are used to reflect back signals down to the earth surface.

Micro-wave communication: Micro-wave is a high frequency electro-magnetic signal which is mostly used in satellite communication.

Geo-stationary satellite are used to accept uploaded signals using uplink frequency and reflect back downloaded signal with downlink frequency.

Transmitter (for uploading) and receiver (for down loading) are faintly available in the form of transceiver medium used by sender or receiver device.

Multiplexing: It is an hardware technique to combine more than one simple signal to form a compo rite carrier signal to be transmitted over network channel.

De-Multiplexing is the reverse process to filter out original simple signal from the comporite carriers on the receiving side.

FDM(Frequnecy Division multiplexing): bandwidth of a network channel: denotes different value in H2 between highest supported frequency range and lowest supported frequency range.

FDM is a technique of combining signal components into one comporite signal, when the channel Bandwidth is higher than the total combine signal bandwidth. So, using signal network channel it is possible to transport set of signal by using a multiplexes hardware.

WDM(wave Division Multiplexing): When optical signal carriers is used to transmit signal as light wave, WDM is used.

These includes combining multiple light signal into one compo rite form using an optical prison, which derives compo rite light wave.

These light wave is transported to receiving side, which de- multiplexes the received signal into individual light waves using another optical prison.

TDM(Time Division Multiplexing):

Synchronous TDM: Here each Host-Machine(sender) is given a fined time-slot, within which the machine can send data over a common network channel TDM multiplexer switches between machine to machine in round robin manner depending on time slot.

Disadvantage:(1) It data transmission is not finish within the time slot for a particular sender, it has to wait before the next chance comes up. It these occurs for many sender will increase system overrate, making system slow.

(2)It sender has nothing to transmit, its time slot is wasted.

Asynchronous Tdm: In asynchronous Tdm. We consider out of n sender not all sender will transmit at the same time. So, no. of time slot is less than n Tdm multiplexer allocate time slot to sender device as per demand.

Advantage: (1) These procedure avoids wastage of time slot and idleness of network channel.

HDLC: (High level data link control): These is a bit oricuted full duplex protocol which is used in a multipoint communication system.

(a) Primary Device- It has right to send data.

(b) Secondary device- it has the right to received data.

(c) Combined device- it is the collection of primary and secondary device.

It is a protocol to present arising errors. It determines where a better msg starts & ends & what part of the msg is included in the CRC. It uses but stuffing for data transferring. Bit stuffing is the method with the help of this are can rectify the ambiguity at data frame if sub string of data matches with the flog bit. Under this mechanism the system will insert a after consecutive five awes. It will malice impossible be find out the flog bit unique.

Project802:IEEE proposed a modification of OSI model by dividing data link layer into two section as action.

(a) Logical link control

(b) Medium access control

These model is called project802 which is mainly used in local area network.

Networking & Internetworking Device:

Networking Device are mostly required in inter-mediate stages in local networking.

Networking Device:

Repeater, Bridge

Internetworking device are mostly required in connecting internal network.

Inter-networking:

Router, gateway

Repeater: It is a connecting device. Which work at physical layer, to regenerate signal strength in case of long distance communication repeater should be install at some distance interval so that original signal can be transported to the receiver. It acts as a regenerate to simplify signal and cut off the noise.

BridgeLConnection of lan)

Bridge is a connecting device which is mainly used to connect Lans. It acts as a repeater when data packet belongs to a neighbouring lan otherwise it can reside destination lan by interacting with other bridges.

Bridge work in data link layer and so it can recognize data link layer address of the transmitted.

Bridge: 1) Simple bridge2) transparent bridge

Simple Bridge: It is a manually operation device where neighboring Lan information are to the entered by an operation Lan logs into network also any division or updation of network device is to the manipulated by an operation.

Transparent Bridge: (It initially has no knowledge about its neighbors when it logs a network by watching different incoming data packet address) it gradually bits it address table.These type of address generation for neighboures is called backwared learning. So in future it will be able to deliver packets to it neighboring Lan.

Router: It is an inter networking device which works in the network layer. Its basic purpose is to route data packets to there destination using network layer address. It uses routing algorithms to decide ideal path so that the packet can reach its destination efficiently. It Router finds the destination address is its neighbours, it simply acts as a bridge.

Router:1) single protocol router2) Multiple protocol router 3) Brouter bridge router.

Single protocol Router: These router can connects distinguish networks which uses similar protocol.

Multiple protocol Router: It can connect different network with variable protocol.

Brouter: It is a combined functionality of a bridge and a Router which is mostly multi protocol Router.

Routing Algorithms: 1) Distance vector Routing: In these algorithm each router maintain a distance vector table which is a table of address for its neighbouring network and routers. All the router are mesh connected so that each router can final several routers to send packet.

The basic activity: 1) Router maintains knowledge about its neighbours.

2) It exchanges information periodically with others which are directly connected.

3) Every router updates its memory table if there is some changes in the network.

4) Link state Routing: In these algorithm every router can share a common data base which stores information abt. Network. The routers are maintaining information about their locality and they also exchange these information with other routers.

The basic activities are:1) The Router keep knowledge about its neighbouring network.

2) Every Router stores its neighbourhood information in UNK state database.

3)Router shares information with other routers only there is change in network.

Routing Process: 1) Adaptive Routing: It means deciding router depending on the present networking condition.

2) Non-Adaptive Routing: It uses fined router which doesnot depends on networking condition.

Gate way: It is an advanced router device which operates in all layers of the OSI interface. It can convert one network protocol to another in case of network to network communication. The basic functions are as follows.

a) It can act as a router.

b) It can convert one network protocol to another.

c) It can send packets to any external network.

d) Network layer protocol:1)ARP 2) RARP 3) ICMP 4)IGMP

ARP: (Address Resolution Protocol) It is a protocol used to find physical address of the host when its internet address is known. In these protocol if a host sends query packet to its server requesting physical address table and response with device address.

RARP: (Reverse ARP) It is a protocol which is used to find internet address of the host when the physical address is known. Here host request it server to send its internet address server find the address and send response.

ICMP: (Internet control Message protocol) It is a protocol used to provides feedback incase of failure in delivery of data packet by any device. In such case the failing device reports back to the predecessor and request for retransmission.

IGMP: (Internet group Message protocol) It is a message bootong protocol where sender can use a) Unicasting- sending message to are receiver.

b) Multicasting: sending message to group of receiver.

c) Broad casting: Sending message to all.

Sonet: (synchronous optical network)It is an example of packet switching optical network which transmits digital data in optical form sonnet uses a special signal called STS which is a high-speed optical signal.

Sonnet device:

1) STS multiplex]

2) STS regenerate

3) STS adol/drop multiplex

STS multiplex: Multiplex takes digital signal uses optical source to generate light wave, converts digital to optical form de-multiplexer perform weres activity.

STS Regenerate: It is use to amplify STS signal for transmission over network.

ADD/Drp mul: These is a foltering device which simple optical signal from a composite.

Sonet layer:1) palk layer- (transport)2) line layer(network)3) section layer(data link)4) photomic layer(physical)

Photomic layer: These is the bottom most layer which provides physical specification about light particle fibre optic channel type of multiplexer used etc.

Line layer: These layer is responsible for resoursing source of destination address and the type of communication channel used.

Palk layer: These layer is responsible transferring digital to optical or digital signal conversion using mux/demux.

Also it is responsible for routing signal user deal router.

X.25:It is an example of packet switching wide area network (WAN) which uses virtual circuite approach tp packet switching.

Physical layer: In these the network uses a protocol called X.21 which consists with specification signal characteristics and grouping of width.

Frame layer: These layer consists construction of frame or packet format using a protocol LAPB (link_Access_Protocol_Balanced) Also, it is responsible for error control and flow control for delivery of data packet.

Frame types: 1) I- frame (Information frame) It carries information about network transport protocol.

5) S- frame(supervisory frame) It carries information about network management.

6) U-frame(Uses frame) It carries information about user data.

Packet layer: These layer is responsible for transporting data packet using a protocol called PLP(packet layer protocol) The protocol uses packet switching with connection establishment virtual circuit creation data transfer connection termination. Each packet contains information about the virtual circuit used.

Q PSK:( Quadrature PSK) IT varies phase change considering for states as O0, Do0 so that use can have four values in the variation of phase.

DISK(Differential PSK) It mixs variation of bit pattern representing phase change in four different states.